Emad M. Arasteh

• Tuesday 10:00am-12:00pm, Keck Center N206
  
• Wednesday 2:00pm-3:00pm, Zoom 924 7459 8913
  

Projects Research Publications Teaching Students Industry Blog Book suggestions

Projects

Ongoing Projects

• Scalable architecture to tackle memory bottleneck in many-core computers
  
  
• Out-of-order parallel SystemC simulation on many-core architectures
  

Completed Projects

• Explore parallelism in system level models by assessing PDES performance (2018-2020, UCI)
  
  
• Controller architecture of enterprise solid state drive (SSD) (Summer 2021, Samsung)
  
  
• ASIC design of speech recognition processor (Summer 2019, Syntiant)
  
  
• ASIC design and verification of network video camera chip (2015-2018, Canon Inc. - Axis Communications)
  
  
• DSP software design of multi-standard 2G/3G/4G cellular modem (2012-2014, Ericsson Modem)
  
  
• Software design for airbag bike helmet (2011-2012, Hövding)
  
  
• ASIC design and verification of Video Display Controller (VDC) (2010-2011, ARM)
  
  

Research

• System-level modeling and design of embedded systems
  
• Deep neural networks
  
• Programming models for processing-in-memory
  
• Simulation of computational models on massively parallel computers
  

Publications

Book Chapters

• E. Arasteh, R. Dömer
  An Untimed SystemC Model of GoogLeNet
  in "Analysis, Estimations, and Applications of Embedded Systems"
  by M. Wehrmeister, M. Kreutz, M. Götz, S. Henkler, A. Pimentel, and A. Rettberg,
  reprint of best papers at IESS 2019, Springer, February 2023. (ISBN: 978-3-031-26499-3)
  
  
• R. Dömer, Z. Cheng, D. Mendoza, E. Arasteh
  Pushing the Limits of Parallel Discrete Event Simulation for SystemC
  in A Journey of Embedded and Cyber-Physical Systems
  by Jian-Jia Chen, Springer Nature, Switzerland, August 2020. (ISBN 978-3-030-47487-4)
  
  

Journals

• E. Arasteh, R. Dömer
  Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention
  Journal of ACM Transactions on Embedded Computing Systems (TECS), Accepted on July 2023.
  
  

Conferences Papers (peer reviewed)

• E. Arasteh, V. Govindasamy, R. Dömer
  BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0,
  Accepted at Design, Automation and Test in Europe (DATE) Conference, Valencia, Spain, March 2024.
  
  
• C. Raccomandato, E. Arasteh, R. Dömer
  MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells
  Proceedings (research track) of the Design and Verification Conference in Europe, Munich, Germany, November 2023.
  
  
• C. Raccomandato, E. Arasteh, R. Dömer
  Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor
  Proceedings (engineering track) of the Design and Verification Conference in Europe, Munich, Germany, November 2023.
  
  
• V. Govindasamy, E. Arasteh, R. Dömer
  Minimizing Memory Contention in an APNG Encoder using a Grid of Processing Cells
  Proceedings of the International Embedded Systems Symposium,
  "Designing Modern Embedded Systems: Software, Hardware, and Applications"
  (ed. S. Henkler, M. Kreutz, M. Wehrmeister, M. Götz, A. Rettberg),
  Springer, Lippstadt, Germany, November 2022.
  
  
• E. Arasteh, R. Dömer
  Improving Parallelism in System Level Models by Assessing PDES Performance
  Proceedings of Forum on Specification and Design Languages, Antibes, France, September 2021.
  
  
• Z. Cheng, E. Arasteh, R. Dömer
  Event Delivery using Prediction for Faster Parallel SystemC Simulation
  Asia and South Pacific Design Automation Conference, Beijing, China, January 2020.
  
  
• D. Mendoza, Z. Cheng, E. Arasteh, R. Dömer
  Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES
  Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, March 2020.
  
  
• E. Arasteh, R. Dömer
  Untimed SystemC Model of GoogLeNet
  Proceedings of the International Embedded Systems Symposium,
  "Embedded Systems: Design, Analysis and Verification"
  (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig),
  Springer, Friedrichshafen, Germany, September 2019.
  
  
  
• Awarded Excellence in Signal Processing Award (ESPA) by Texas Instruments:
  E. Arasteh, I. Mohajeri
  Implementation and Hardware Approach to MIDI-Synthesizer using DSP TMS320C6713
  Swedish System-on-Chip Conference, Arild, Sweden, May 2009.
  
  

Technical Reports

• N. Farzan, E. Arasteh
  Visualizing Transaction-Level Modeling Simulations of Deep Neural Networks
  Fowler School of Engineering, Technical Report 23-01, August 2023.
  
  
• E. Arasteh, R. Dömer
  Systematic Evaluation of Six Models of GoogLeNet using PDES
  Center for Embedded and Cyber-Physical Systems, Technical Report 21-03, September 2021.
  
  

Theses

• E. Arasteh
  Transaction-Level Modeling of Deep Neural Networks for Efficient Parallelism and Memory Accuracy
  Ph.D. Thesis, University of California, Irvine, July 2022.
  
  
• E. Arasteh
  AMBA AXI Video Display Controller Supporting Paged Memory
  Master Thesis, Lund University, Sweden, February 2011.
  
  

Recent Invited Talks and Presentations

• E. Arasteh:
  "System Level Modeling and Simulation: Designing Future Computer Systems",
  Presentation at Road to Research Seminar Series, Fowler School of Egnineering, Chapman University, October 2022.
  
  
• E. Arasteh:
  "Explore Parallelism and Memory Contention in System Level Models by Assessing PDES Performance",
  Poster Presentation at PhD Forum at Design Automation Conference, San Francisco, California, July 2022.
  
  
• E. Arasteh:
  "Exploration of Memory-Accurate Models at Different Levels of Abstraction",
  AMD Research, Advanced Intelligent Memory Group, United States, January 2022.
  
  

Teaching

Students

• Nataniel Farzan (farzan@chapman.edu)

Industry Experience

Digital Hardware Designer, M.Sc. Thesis (2010-2011)

Embedded Software Engineer (2011-2012)

ASIC Engineer and DSP Developer (2012-2014)

Experienced ASIC Engineer (2015-2018)

Hardware Engineering Intern (Summer 2019)

System Architecture Intern (Summer 2021)

Research Funding Entity, Ph.D. Thesis