Emad M. Arasteh

Emad M. Arasteh

Address:	Emad M. Arasteh Assistant Professor Electrical Engineering and Computer Science Dale E. and Sarah Ann Fowler School of Engineering Chapman University Orange, CA 92866 USA
Office:	Swenson Hall of Engineering N325
Email:	arasteh@chapman.edu
Phone:	+1 (714) 516-5215
WWW:	https://www1.chapman.edu/~arasteh/

Lab:	System Platform Exploration Lab (SPEL) Swenson Hall of Engineering N230D

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Office hours
Tuesday 10:00am-11:15am,	Keck Center N204
Wednesday 2:00pm-4:15pm,	Keck Center N206

Projects Research Publications Teaching Students Industry Blog Book suggestions

Projects

Ongoing Projects

Scalable architecture to tackle memory bottleneck in many-core computers

Out-of-order parallel SystemC simulation on many-core architectures

Completed Projects

Explore parallelism in system level models by assessing PDES performance (2018-2020, UCI)

Controller architecture of enterprise solid state drive (SSD) (Summer 2021, Samsung)

ASIC design of speech recognition processor (Summer 2019, Syntiant)

ASIC design and verification of network video camera chip (2015-2018, Canon Inc. - Axis Communications)

DSP software design of multi-standard 2G/3G/4G cellular modem (2012-2014, Ericsson Modem)

Software design for airbag bike helmet (2011-2012, Hövding)

ASIC design and verification of Video Display Controller (VDC) (2010-2011, ARM)

Research

System-level modeling and design of embedded systems

Deep neural networks

Programming models for processing-in-memory

Internet of Things (IoT)

Short Biography

Publications

Selected Publications

E. Arasteh, R. Dömer
Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention
ACM Transactions on Embedded Computing Systems (TECS),
vol. 23, issue 5, article 75, 32 pages, August 2024.

E. Arasteh, V. Govindasamy, R. Dömer
BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0
Proceedings of Design, Automation and Test in Europe (DATE) Conference,
Valencia, Spain, March 2024.

E. Arasteh, R. Dömer
Untimed SystemC Model of GoogLeNet
Proceedings of the International Embedded Systems Symposium,
"Embedded Systems: Design, Analysis and Verification"
(ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig),
Springer, Friedrichshafen, Germany, September 2019.

All Publications

listed by publication type

Recent Invited Talks and Presentations

E. Arasteh:
"SystemC TLM-2.0 Loosely-Timed Contention-Aware Modeling",
Presentation at SystemC Evolution Day 2024,
Munich, Germnay,
October 2024.

E. Arasteh:
"System Level Modeling and Simulation: Designing Future Computer Systems",
Presentation at Road to Research Seminar Series,
Fowler School of Egnineering, Chapman,
October 2022.

E. Arasteh:
"Explore Parallelism and Memory Contention in System Level Models by Assessing PDES Performance",
PhD Forum at Design Automation Conference (DAC),
San Francisco, CA,
July 2022.

E. Arasteh:
"Exploration of Memory-Accurate Models at Different Levels of Abstraction",
AMD Research, Advanced Intelligent Memory Group,
United States,
January 2022.

Teaching

Current Courses
F24:	CENG 231,	Systems Programming
F24:	CENG 231L,	Lab - Systems Programming
F24:	CENG 381,	Modeling and Simulation
Recent Courses
S24:	CENG 231,	Systems Programming
S24:	CENG 231L,	Lab - Systems Programming
Courses at Chapman
Courses at UC Irvine

Students

Undergraduate Students
Nataniel Farzan	Computer Science (2026)	(farzan@chapman.edu)
Ewan Shen	Computer Science (2025)	(ewshen@chapman.edu)
Maha Bhatti	Data Science (2026)	(mbhatti@chapman.edu)

Industry Experience

Digital Hardware Designer,
M.Sc. Thesis (2010-2011)

Embedded Software Engineer
(2011-2012)

ASIC Engineer and DSP Developer
(2012-2014)

Experienced ASIC Engineer
(2015-2018)

Hardware Engineering Intern
(Summer 2019)

System Architecture Intern
(Summer 2021)

Research Funding Entity, Ph.D. Thesis

August 26 2024 E. Arasteh (arasteh@chapman.edu).