CPSC466 Integrated Circuits Design II
Fall 2005
·
Text book: Introduction
to VLSI Circuits and Systems
Introduction
Digital-logic
CMOS-layers
Transistor-sizing
MOS-Electrical-Characteristics
Homework1-solution
Homework2-solution
HW3
HW4
Labs
Lab1 Path Setup, Magic
tutorial
·
Magic
·
Magic
brief overview http://vlsi.ece.iit.edu/scells/ece429/MAGIC1x.html
·
Magic inverter tutorial http://vlsi.ece.iit.edu/scells/magic/
Lab2 Stick diagram
Lab3 Circuit extraction and HSPICE
Lab4 Circuit
simulation and optimization using Hspice and Awave from Synopsys
Hspice
input file: right click and download, then put in your directory
AWAVE
to view output
Hspice Awave tutorial (good)
Spice
Analysis Manual
Lab5 Latch and
Flip-Flop Simulation with Unix Shell
Lab6 Decoder
design due Dec.3
Lab7 MOSIS pad frame
and CIF file for chip fabrication
Magic Tape
out notes
How
to use the pads
Create
MOSIS account, MOSIS
Customer Agreements and Access Forms
MOSIS Reference Library:
MOSIS FAQs,
MOSIS Technical Notes, Resources on the Internet, VLSI Text Book
Recommendations
VLSI CLASSES OF OTHER UNIVERSITIES
·
University
of Stanford ee 371 , Stanford VLSI
research projects
·
University of
Southern California, Dr. Pedram Low Power design
·
Courses
at MIT: http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/index.htm
·
EDA lab by Dr. Lei He ,
UCLA (Leakage, layout and power estimation)
·
Dr.
A. Mason EE 410S05 Very good link!
·
ECE 425 by Dr. John
A. Nestor http://foghorn.cadlab.lafayette.edu/ece425/index.html
·
http://www.rose-hulman.edu/~simoni/Classes/EC551/ec551.html
·
Computer
Architecture, Arithmetic and CAD Research Group at by Dr. James Stine
·
Harvey
Mudd College
CMOS VLSI Design, A Circuits and Systems
Perspective book website
·
Cadence
Repository for Electronic Technical Education
·
·
University of
Tennessee: 12-cell
standard cell library which can be fabricated on the
MOSIS educational runs
·
Olin College VLSI
HSPICE/ SPECTRE
· HSPICE Tips Document by Rhett Davis from UC
Berkeley eece 141
· HSPICE tutorial
http://homepages.cae.wisc.edu/~kime/555/tutorials/hspice/spc_tut.pdf
· A brief guide to HSPICE: sweep , find-when, etc
http://www.ee.tufts.edu/r/nanolab/hspice.html
· Measuring Digital Properties using Spectre
http://www.ece.iit.edu/~vlsi/cadence/spectre4.html
VLSI Design Flow
·
Top
down Standard cell ASIC design: How to use a Standard
cell (ASIC) Design approach (vhdl or verilog to physical)
·
Bottom
up Full Custom design: Tale of an IC
Engineer
·
Design
flow (HDL and chip level )
·
Design
flow (logical physical level
·
Jazz Foundry Assisted COT design flow: http://www.jazzsemi.com/images/process_technologies/FAsCOT-Flow.gif
STANDARD CELL LIBRARY
·
Survey
of standard cell libraries by Graham Petley
·
Links from IIT
·
Creating a
LEF file for Silicon Ensemble from IIT
·
From stick diagram to layout: http://www.stanford.edu/class/ee271/stick_to_layout/stick_to_layout.html
·
Layout suggestions:
http://bwrc.eecs.berkeley.edu/Classes/ICDesign/ee141_f01/grade/faq/layout_common_sense.htm
·
Tutorial for Standard Cells Library from
http://www.cs.utah.edu/classes/cs5710/tutorials/tutorial03.htm
Electric Circuit
·
Fundamentals
of Electric Circuits MHHE Online Product Registration
·
Electric circuits introduction
Other links
·
IEEE
Transaction on Very Large Integrated Systems
submission
·
IEEE International Symposium of Circuits and Systems: http://www.slrc.kyushu-u.ac.jp/iscas05/
·
IEEE Microelectronics Education Conference: www.mseconference.org/mse05cfp.pdf
·
ICSVLSI – IEEE Computer Society Annual Symposium on VLSI
·
IEEE International
·
System On Chip 03: http://www.savantcompany.com/SoC3-Fall2005/agenda3.htm
·
Gigascale Silicon Research Center at Berkeley
·
Programmable
System-on-a-Chip
·
MicroSystems Research Laboratory at Penn State
·
VLSI Research Group
University of Toronto
·
MPL's SCMOS RELEASE (Microsystems Prototyping Laboratory)
·
Magic
·
MOSIS
·
Semiconductor Research
Corporation
·
Semiconductor Industry
Association
Peiyi Zhao
Department of Math and
Computer Science
Wilkinson College of Letters & Sciences
