Teaching

Research

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Research Publications:

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JOURNAL PUBLICATION:

·         P. Zhao, Jason McNeely, Weidong Kuang, Zhongfeng Wang, “Design of Sequential Elements for Low Power Clocking System”  IEEE Transacting on Very Large Scale Integration (VLSI) system, vol. 19, no.5, pp. 914 – 918, May 2011(Top 18 most downloaded papers in IEEE Transaction on VLSI in 2011)  
G scholar citation: 76 times

·         W. Kuang, P. Zhao, J.S.Yuan, and R. DeMara, “Design of asynchronous circuits for high soft error tolerance in deep submicron CMOS circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.3, pp.410-422, March 2010

·         P. Zhao, J. McNeely, S. Venigalla, G. P. Kumar, N.Wang, M. Bayoumi, W. Kuang, and L. Downey, “Low Power Clocked-Pseudo-NMOS Flip-flops for Level Conversion in Dual Supply Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17,  Issue 9,  pp.1196 – 1202, Sept. 2009. (Cited by text book: CMOS VLSI Design, N.Weste, D.Harris, Pearson, 4th edition, 2010 )
G scholar citation:  50 times

·         P. Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Kuang W.D, and Robert Barcenas,Low Power Clock Branch Sharing Double-Edge Triggered Flisp-Flop, IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol.15, No.3, pp. 338-345, March 2007. (Cited by text book: CMOS VLSI Design, N.Weste, D.Harris, Pearson, 4th edition, 2010)
 
G scholar citation: 81 times

·         P. Zhao, T. Darwish, M. Bayoumi, “High Performance and Low Power Conditional Discharge Flip-Flop,”   in IEEE(Institute of Electrical and Electronics Engineers) Transactions on Very Large Scale Integration (VLSI) Systems, Vol.12., No. 5, pp. 477-484, May 2004
G scholar citation: 216

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PATENT             
U.S. Patent:
“Single-transistor-clocked flip-flop,” P. Zhao, T. Darwish, M. Bayoumi

 

CONFERENCE PUBLICATIONS (presentations):

G. Hang, Y. Yang, P. Zhao, X.Hu, X. You, “A Clocked Differential Switch Logic Using Floating-Gate MOS Transistors,  IEEE the10th International Conference on ASICON, Oct. 28-31, 2013, Shenzhen, China.

G. Hang , H.Zhu, P. Zhao, X.Zhou,  “Adjustable Schmitt triggers using floating-gate MOS transistors” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),  Oct. 29 -Nov. 1, 2012, Xi’an, China.

 

G. Hang, P. Zhao, “Novel CMOS Schmitt triggers using floating-gate MOS transistors”, IEEE International ASICON Conference, Oct.25-28, 2011, Xiamen, China.

P.Zhao, Z.Wang, “Power Optimization for VLSI Circuits and Systems,” IEEE  10th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010), Nov.1-4, Shanghai, China(Invited talk, Session chair, TPC member).

 

P.Zhao, Z.Wang, “Low Power Design of VLSI Circuits and Systems”, IEEE ASICON, Oct.20-23, 2009, Changsha, China(Invited talk).

 

P. Zhao, Drew Moshier, Michael Fahy, “Incorporating Real World Integrated Circuit in a Liberal Arts Computer Science Program”, IEEE International Microelectronics System Education Conference(MSE09), July 25-27, 2009, San Francisco, CA.

 

P. Zhao, J. McNeely, Pradeep Golconda, Magdy A. Bayoumi, Bob Barcenas, Jianping Hu, “Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors,” IEEE International Conference on Circuits & Systems for Communications(ICCSC08), May 26-28, 2008, Shanghai, China.

P. Zhao, J. McNeely, G. P. Kumar  and M. Bayoumi,  “Low Power Keeper for High Fan-In Domino Circuits,” in IEEE International Symposium on Circuits and Systems(ISCAS 2007), May 27-30, 2007, New Orleans,  LA.


Md Faisal, P. Zhao, M. Bayoumi, “A Low-Power Clock Frequency Multiplier,” IEEE International Symposium on Circuits and Systems(ISCAS 2006), May 21-24, 2006, Kos, Greece

P. Zhao, G. P. Kumar, Jason M. and M. Bayoumi, “External- Internal Dual Switch Leakage Controlled Flip-flop design,” IEEE International Mid West Symposium on Circuits and Systems(MWSCAS 2005), August 10, 2005, Cincinnati, Ohio

P. Zhao, G. P. Kumar and M. Bayoumi, “Contention Reduced/Conditional Discharge Flip-Flops for Level Conversion in CVS Systems,” IEEE International Symposium on Circuits and Systems (ISCAS 2004), May 23-26, 2004, Vancouver, British Columbia, Canada.

P. Zhao, G. P. Kumar, A. Chidanandan and M. Bayoumi, “A Double-Edge Implicit-Pulsed Level Convert Flip-Flop,” IEEE Computer Society Symposium on VLSI (ISVLSI04), February 19-20, 2004, Lafayette, Louisiana, pp. 141-144. (Presentation acceptance rate: 23%)

P. Zhao,T.Darwash, and M. Bayoumi, “Low Power Conditional-Execution Pulsed Flip-Flop,” IEEE Computer Society, Looking Forward Magazine, Summer 2003.

P. Zhao, T. Darwish, M. Bayoumi, “Low Power and High Speed Explicit-Pulsed Flip-Flops,” 45th IEEE International Midwest Symposium on Circuits and Systems Conference (MWSCAS02), Tulsa, Oklahoma, August 4-7, 2002, vol.2, pp.477-480.           

General Research Information:

Research Interest

·         Low power clocking circuits design, Clock gating, Low leakage circuits

·         Ultra low power circuits for micro-controllers in wireless sensor network

·          Soft error (radiation hardening )

People in Related Research Area: 
                         
Dr. Bouldin Don    http://web.eecs.utk.edu/~bouldin/
                          Dr. Pat Gelsinger, former Intel CTO, currently CEO of VMware. He was the architect of the original 80486 processor. His website is here:
http://www.patgelsinger.com/       

                         Dr. Donald Lie, http://www.tturfsoc.com/Pages/research.php                                  

Study and Research Websites

IEEE Xplore

ISI Web of Science

Proquest Digital Thesis Data Base      
Wangfang  Data Base           

 

Check what others have asked: Internet FAQ Archives

Google Scholar

Google Answers

Google Groups

Yahoo Group (VLSI, HDL, etc)

How Stuff Works

Research tips: SCAN(cited from Peiyi Zhao’s Ph.D thesis)

Survey existing research     
Categorize them into groups             
Analyze advantage and drawback  
New design proposal

                        Research notes by Dr. Yu Wang

VLSI CAD Links

Altera

Atmel

Cadence Help

Cadence Home Page

Magic VLSI Layout Tool

Modelsim

Synopsis

Xilinx

 

Peiyi Zhao

Associate Professor,  

School of Computational Science

Chapman University

One University Drive, Orange, CA 92866