Peiyi Zhao, Ph.d

Teaching:

CENG 465 Integrated Circuit Design

EENG 541 Advanced integrated circuit (Graduate level class) CPSC 298 Digital Integrated Circuit (Computer Science Colloquium) CENG 330 Digital Logic Design I CENG 366 Digital Logic Design II CENG 351 Computer Architecture

News: 2025: Final project of CENG465 Integrated circuit design: translate flip flop schematics in IEEE papers to layout, pass DRC/LVS,verify waveform, measure power consumption using Cadence, Siemens, Synopsys tools. A few student webpages:

https://students.chapman.edu/~azagorski/

https://students.chapman.edu/~jgarcia2/Final_Project_Report.pdf#zoom=FitV

2024: NSF panelist, 4 times 2023: One paper published in IEEE Transaction on VLSI , May 2023! * An advanced technology, 22nm technology, is used in the above paper

* Cadence, Mentor Graphics (Simens) Calibre, Synopsys Hspice tools are used in the research project for the above paper

o The above tools are used in CENG 465 Integrated Circuit I class

* Students in Computer Engineering and Electrical Engineering are involved in the above research project and joint authors of the paper. 2022: * Obtained 22nm technology PDK after Office of Research signed an NDA * One paper submitted to IEEE Transaction on VLSI, after overcoming the challenges related to NDA, PDK and tools.

* Microelectronics/Semiconductor (subject area of Computer Engineering/Electrical Engineering) related news

The CHIPS Act (Creating Helpful Incentives to Produce Semiconductors for America Act, Aug.2022) and its programs are expected to create many tens of thousands of new jobs in semiconductor manufacturing and R&D over the next few years.
https://blogs.berkeley.edu/2022/08/09/chips-act-includes-new-support-for-workforce-training-providing-opportunities-beyond-rd-for-higher-education/

National Science Foundation (NSF) Integrated Circuit Research, Education and Workforce Development Workshop Final Report reads: "it demands that we figure out how to rapidly triple qualified [Semiconductor /Microelectronic] candidates even as there are 15% fewer [ college-aged individuals] ", source: paragraph 3 of page 18, https://nsf-ic-education.com/report/ , May 2022

In terms of the regional jobs in semiconductor, Orange County was ranked as high as the No. 2 county in California in the past 10 years, https://www.ocbj.com/LEADER-BOARD/ORANGE-COUNTY-CAN-BENEFIT-FROM-CHIPS-ACT/ , Oct.2022

2021: Seeking access to PDKs of industry 45nm- or-below technologies 2020: Covid 19, research stopped 2019: Call for papers: The IEEE International Workshop on Signal Processing Systems http://sips2019.org/

The IEEE International Workshop on Signal Processing Systems is a major international forum for discussion of new technology progress and innovations in the design and implementation of digital signal processing systems. It addresses all aspects of architecture and design methods of these systems. Emphasis is on current and future challenges in research and development in both academia and industry.

2019: Used PDK of an educational 45nm technology. One paper submitted to IEEE TCAS II received revision notice.

2018: Caliber integrated into Virtuoso 2017: Mentor Graphics setup. 2016: Virtuoso layout tool of Cadence installed 2013-2014: Changed to use MicroMagic layout tool (Changed to use Cadence after 2015) 2011: Our paper, “Design of Sequential Elements for Low Power Clocking System”, has been listed as the top 18 most downloaded paper in IEEE Transaction on Very Large Scale Integration (TVLSI) in 2011

2010: Two diagrams of our low power VLSI designs have been included in VLSI textbook, CMOS VLSI Design, by N.Weste, David Harris, Pearson, Fourth edition, March 2010.

Former students (not a complete list):

Samuel Bernsen (2025), Siemens Luke Valerio (2025), graduate program in Washington University Nicholas Mirchandani (2022), SpaceX Eric Lim (2020), Amazon Robert Barcenas (2007), Siemens, memory circuit design

Pradeep Golconda, Intel Soujanya Venigalla, Intel