News
2026
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Electrical Engineering Undergraduate Student Luke Valerio in CENG 465 Integrated Circuit I Spring 2025 class completed a final project using industry-standard chip design tools to implement circuits from 2021 IEEE Journal papers at layout level:
https://lukeval27.github.io/ICFinalProjects/
(the website was setup in Nov. 2025). He began his graduate studies in University of Washington in Fall 2025, and secured a position as Physical Design Engineer at Apple in July 2026
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Jonathan Terbush, an EECS master's thesis student, received the Nachman Family Innovation Challenge Award
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Polukh Polukhov, an EECS master's thesis student, published a paper in IEEE FiCloud (EMSICC) 2026.
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Set up the SkyWater 130nm PDK for the RTL-to-GDS flow
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Reviewer for the book:"RISC-V System-on-Chip Design" Authors: David Harris, James Stine, Sarah Harris, Rose Thompson; Publisher: Morgan Kaufmann (Elsevier) 2026
2025
Final project of CENG 465 Integrated Circuit Design: translate flip-flop
schematics in IEEE papers to layout, pass DRC/LVS, verify waveforms,
and measure power consumption using Cadence, Siemens, and Synopsys tools.
A few student webpages:
2024
NSF panelist four times.
2023
One paper published in IEEE Transactions on VLSI in May 2023.
An advanced 22 nm technology was used in the paper.
Cadence, Mentor Graphics Siemens Calibre, and Synopsys HSPICE tools
were used in the research project.
The tools are also used in the CENG 465 Integrated Circuit Design class.
Students in Computer Engineering and Electrical Engineering participated
in the research project and were joint authors of the paper.
2022
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Obtained a 22 nm technology PDK after the Office of Research
signed an NDA.
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One paper submitted to
IEEE Transactions on VLSI after overcoming challenges
related to the NDA, PDK, and tools.
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Microelectronics and semiconductor-related news:
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The CHIPS Act — The Creating Helpful Incentives
to Produce Semiconductors for America Act, enacted in August 2022,
is expected to create many tens of thousands of new jobs in
semiconductor manufacturing and research and development.
Berkeley: CHIPS Act workforce training
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National Science Foundation Integrated Circuit Research,
Education and Workforce Development Workshop Final Report
reads:
“It demands that we figure out how to rapidly triple qualified
semiconductor and microelectronic candidates even as there are
15% fewer college-aged individuals.”
NSF workshop report
— May 2022
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Orange County was ranked as high as the number two county in
California for regional semiconductor jobs during the past
ten years.
Orange County semiconductor jobs
— October 2022
2021
Seeking access to PDKs for industry 45 nm-or-below technologies.
Office moved into new building, Swenson Hall
2020
COVID-19; research stopped.
2019
Used the PDK of an educational 45 nm technology.
Fowler School of Engineering was launched.
Call for papers:
IEEE International Workshop on Signal Processing Systems
The IEEE International Workshop on Signal Processing Systems is a
major international forum for discussion of new technology progress
and innovations in the design and implementation of digital signal
processing systems. It addresses all aspects of architecture and
design methods of these systems. Emphasis is on current and future
challenges in research and development in both academia and industry.
Used the PDK of an educational 45 nm technology. One paper submitted
to IEEE TCAS II received a revision notice.
2018
Calibre integrated into Virtuoso.
2017
Mentor Graphics setup.
2016
Virtuoso layout tool from Cadence installed.
2013–2014
Changed to use the MicroMagic layout tool. Changed to Cadence after 2015.
2011
Our paper, “Design of Sequential Elements for Low Power Clocking
System,” was listed among the 18 most downloaded papers in
IEEE Transactions on Very Large Scale Integration (TVLSI)
in 2011.
2010
Two diagrams of our low-power VLSI designs were included in the VLSI
textbook CMOS VLSI Design, by N. Weste and David Harris,
Pearson, fourth edition, March 2010.