CPSC330 Digital Logic

 

1.     Syllabus

2.     Course information

Chapter

Topics(tentative)

 Lab(tentative)

 

1 From zero
to one

               Introduction: market, design challenge

 

 

 

 Lab 1:Inverter: Magic VLSI Layout tutorial:
www.chapman.edu/~zhao/CPSC330-365/lab-Magic-layout.ppt

Lab2 Circuit simulation and optimization using Hspice and Awave from Synopsys

 

Car seat belt, motion detect,  door bell, automatic garage door system

6 levels computer

1.4: number system: binary, binary numbers; bits, bytes, and nibbles ;hex,signed binary, two’s complement. To find 2’s compl of negative num:find the equivalent binary of the magnitude, invert each bit, add 1. 

 

1.5: Logic gate: car seat belt example, motion-in-dark example, etc
     Logic Levels; Transistor-level implementation; truth tables,minterm(product involving all the inputs), Boolean expressions(summing  each of  the minterms for which the output of that row is True );  Boolean Algebra

 

1.6 Beneath the digital abstraction

 

Verilog Introduction(slides 1-19) coursey: Lysecky. Or read book: Chapter 4:4.1

1.7 CMOS transistor (CMOS NOT, NAND gate)

 

1.8 Power Consumption

 

2 Combinational Logic Design

2.1 Introduction
2.2 Boolean Equations

2.3 Boolean Algebra
Duality: if the symbols of 0 and 1 and the operators *(AND)
 and +(OR) are interchanged, the statement will still be correct.
DeMorgan’s theorem: bar(A*B)
=bar_A+bar_B, bar(A+B)=bar_A*bar_B
2.4 From Logic to Gates 
2.5 Multilevel Combinational Logic
2.6 X's and Z's, floating value: tri-state design,

2.7 Karnaugh Maps
2.8 Combinational Building Blocks


Verilog Hardware Programming Language:

Chapter 4: http://www.chapman.edu/~zhao/CPSC330-365/Ch4-Verilog-DDCA.ppt

4.2 Verilog Combinational Logic Verilog :Combinational Circuits(slides 20-42)

 

Midterm

 

Lab3 Xilinx 8.1 Simulation,  Courtesy Dr. Lysecky

Lab4 Xilinx 8.1 Synthesis, Courtesy Dr. Lysecky

 

 

 

 

Lab5: Introduction to Verilog Simulation and Synthesis(AND, OR gates)
  

Lab6: Decoder

Lab7: Seven-segment display(procedure:1-3 only)
         Note: do not name Verilog file that start with number

3 Sequential Logic Design

 

3.1 Introduction
Latch and flip flop

Finite state machine

Verilog Hardware Programming Language:

 

 


Lab8: Counter

Lab 9(tentative): Traffic light

 

4 Hardware Design Language

 Incorporated into corresponding chapters respectively