Book Chapters

E. Arasteh, R. Dömer An Untimed SystemC Model of GoogLeNet in "Analysis, Estimations, and Applications of Embedded Systems" by M. Wehrmeister, M. Kreutz, M. Götz, S. Henkler, A. Pimentel, and A. Rettberg, reprint of best papers at IESS 2019, Springer, February 2023. (ISBN: 978-3-031-26499-3)

R. Dömer, Z. Cheng, D. Mendoza, E. Arasteh Pushing the Limits of Parallel Discrete Event Simulation for SystemC in A Journey of Embedded and Cyber-Physical Systems by Jian-Jia Chen, Springer Nature, Switzerland, August 2020. (ISBN 978-3-030-47487-4)

Journals

E. Arasteh, R. Dömer Fast Loosely-Timed Deep Neural Network Models with Accurate Memory Contention ACM Transactions on Embedded Computing Systems (TECS), vol. 23, issue 5, article 75, 32 pages, August 2024.

Conferences Papers (peer reviewed)

M. Bhatti, E. Arasteh Performance Prediction of SystemC TLM-2.0 Contention-Aware DNN Models Accepted at IEEE International Conference on Omni-layer Intelligent Systems (COINS), Madison, Wisconsin, August 2025.

E. Arasteh, V. Govindasamy, R. Dömer BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0 Proceedings of Design, Automation and Test in Europe (DATE) Conference, Valencia, Spain, March 2024.

C. Raccomandato, E. Arasteh, R. Dömer MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells Proceedings (research track) of the Design and Verification Conference in Europe, Munich, Germany, November 2023.

C. Raccomandato, E. Arasteh, R. Dömer Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor Proceedings (engineering track) of the Design and Verification Conference in Europe, Munich, Germany, November 2023.

V. Govindasamy, E. Arasteh, R. Dömer Minimizing Memory Contention in an APNG Encoder using a Grid of Processing Cells Proceedings of the International Embedded Systems Symposium, "Designing Modern Embedded Systems: Software, Hardware, and Applications" (ed. S. Henkler, M. Kreutz, M. Wehrmeister, M. Götz, A. Rettberg), Springer, Lippstadt, Germany, November 2022.

E. Arasteh, R. Dömer Improving Parallelism in System Level Models by Assessing PDES Performance Proceedings of Forum on Specification and Design Languages, Antibes, France, September 2021.

Z. Cheng, E. Arasteh, R. Dömer Event Delivery using Prediction for Faster Parallel SystemC Simulation Asia and South Pacific Design Automation Conference, Beijing, China, January 2020.

D. Mendoza, Z. Cheng, E. Arasteh, R. Dömer Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES Design, Automation and Test in Europe (DATE) Conference, Grenoble, France, March 2020.

E. Arasteh, R. Dömer Untimed SystemC Model of GoogLeNet Proceedings of the International Embedded Systems Symposium, "Embedded Systems: Design, Analysis and Verification" (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig), Springer, Friedrichshafen, Germany, September 2019.

Awarded Excellence in Signal Processing Award (ESPA) by Texas Instruments: E. Arasteh, I. Mohajeri Implementation and Hardware Approach to MIDI-Synthesizer using DSP TMS320C6713 Swedish System-on-Chip Conference, Arild, Sweden, May 2009.

Technical Reports

N. Farzan, E. Arasteh Visualizing Transaction-Level Modeling Simulations of Deep Neural Networks Fowler School of Engineering, Technical Report 23-01, August 2023.

E. Arasteh, R. Dömer Systematic Evaluation of Six Models of GoogLeNet using PDES Center for Embedded and Cyber-Physical Systems, Technical Report 21-03, September 2021.

Theses

E. Arasteh Transaction-Level Modeling of Deep Neural Networks for Efficient Parallelism and Memory Accuracy Ph.D. Thesis, University of California, Irvine, July 2022.

E. Arasteh AMBA AXI Video Display Controller Supporting Paged Memory Master Thesis, Lund University, Sweden, February 2011.